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• The iMPACT - Welcome to iMPACT window opens. NOTE If the iMPACT - Welcome to iMPACT window does not open, launch iMPACT by selecting Start»Programs»Xilinx ISE Design Suite»ISE»Accessories»iMPACT. If you are prompted to create a new.jpf file, click Cancel. In the Flows pane, double-click PROM File Formatter. The iMPACT - Prepare PROM.

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1. Running an Example Project

For this example, you can download the example program demo.ise, linked at the bottom of the page. To run a project, connect the USB cable to the NI Digital Electronics FPGA Board, apply power to the board, move the power switch to the ON position, and complete the following steps.

1. Launch Xilinx ISE.

2. Select File»Open Project and navigate to the location of demo.ise. Click OK.

3. In the Processes pane of the project window, expand Configure Target Device.

4. Double-click Manage Configuration Project (iMPACT) , as shown in the following figure.

demo.ise Project Window (Design Summary)

The Transcript pane of the project window displays the configuration progress. The compilation will take several minutes. Once compiled, the iMPACT - Welcome to iMPACT window will open.

NOTE If the iMPACT - Welcome to iMPACT window does not open, launch iMPACT by selecting Start»Programs»Xilinx ISE Design Suite»ISE»Accessories»iMPACT.

5. Select Configure devices using Boundary-Scan (JTAG) and Automatically connect to a cable and identify Boundary-Scan chain (these should be selected by default). Click Finish. The Assign New Configuration File window will open.

6. Select the main.bit configuration file in the Assign New Configuration File window. Click Open.

You have the option of selecting additional configuration files. Because you do not need a new configuration, click Cancel. The Device Programming Properties window will open.

7. In the Device Programming Properties window, select Device 1 (FPGA, xc3s500e) to program Device 1. The Digital Electronics FPGA Board FPGA is a Xilinx XC3S500E Spartan-3E FPGA.

8. Click OK. The Boundary Scan pane will open in the project window.

9. Right-click the xc3s500e main.bit icon and select Program.

demo.ise Project Window (Boundary Scan)

After the FPGA successfully programs, the Boundary Scan pane will display Program Succeeded. The FPGA application is now executing on the board.

10. Select File»Close Project. Do not save changes.

2. Verifying the Onboard Flash PROM

For this example, download the example program prom.ise, linked at the bottom of the page. You can use this example program to learn how to verify that a program works before programming the onboard serial platform flash PROM on the NI Digital Electronics FPGA Board. To verify this program, connect the USB cable to the Digital Electronics FPGA Board, apply power to the board, move the Power Switch to the ON position, and complete the following steps.

1. Launch Xilinx ISE.

2. Select File»Open Project and navigate to the location of prom.ise. Click OK.

3. In the Sources pane of the project window, double-click main - Behavioral (main.vhd). The main.vhd code will open in the main pane, as shown in the following figure.

prom.ise Project Window (main.vhd)

You can scroll down the main.vhd pane to find the following example program.

entity main is

Port (

btn : in STD_LOGIC_VECTOR (3 downto 0);

led : out STD_LOGIC_VECTOR (3 downto 0));

end main;

architecture Behavioral of main is

begin

led(0) <= btn(0);

led(1) <= btn(1);

led(2) <= btn(2);

led(3) <= btn(3);

end Behavioral;

4. In the Sources pane, double-click ElvisFpga.ucf (ElvisFpga.ucf), the UCF file associated with prom.ise.

5. In the Processes pane, expand User Constraints, then double-click Edit Constraints (Text).

The ElvisFpga.ucf file contains the following declarations in the Processes pane:

NET led<0> LOC = 'C11' IOSTANDARD = LVTTL SLEW = SLOW DRIVE = 8 ;

NET led<1> LOC = 'D11' IOSTANDARD = LVTTL SLEW = SLOW DRIVE = 8 ;

NET led<2> LOC = 'B11' IOSTANDARD = LVTTL SLEW = SLOW DRIVE = 8 ;

NET led<3> LOC = 'A12' IOSTANDARD = LVTTL SLEW = SLOW DRIVE = 8 ;

NET btn<0> LOC = 'C13' IOSTANDARD = LVTTL PULLDOWN ;

NET btn<1> LOC = 'D12' IOSTANDARD = LVTTL PULLDOWN ;

NET btn<2> LOC = 'C12' IOSTANDARD = LVTTL PULLDOWN ;

NET btn<3> LOC = 'C10' IOSTANDARD = LVTTL PULLDOWN ;

6. Select File»Save All.

3. Testing the Program on the FPGA

To ensure that the program runs well on the FPGA, complete the following steps.

1. In the Sources panel, select the Sources tab, then select main - Behavioral (main.vhd).

2. In the Processes pane, expand and double-click Configure Target Device. This updates all question marks, , with checkmarks, , indicating the successful configuration and generation of files and associated devices.

The Transcript pane of the project window displays the configuration progress. The compilation takes several minutes.

The iMPACT - Welcome to iMPACT window will open.

NOTE If the iMPACT - Welcome to iMPACT window does not open, launch iMPACT by selecting Start»Programs»Xilinx ISE Design Suite»ISE»Accessories»iMPACT.

3. Select Configure devices using Boundary-Scan (JTAG) andAutomatically connect to a cable and identify Boundary-Scan chain (these should be selected by default). Click Finish. The Assign New Configuration File window will open.

4. Select the main.bit configuration file in the Assign New Configuration File window. Click Open.

You have the option of selecting additional configuration files. Because you do not need a new configuration, click Cancel. The Device Programming Properties window will open.

5. In the Device Programming Properties window, select Device 1 (FPGA, xc3s500e) to program Device 1. xc3s500e refers to the Xilinx XC3S500E Spartan-3E FPGA on the Digital Electronics FPGA Board.

6. Click OK. The Boundary Scan pane will open in the project window.

7. Right-click the xc3s500e main.bit icon and select Program.

prom.ise Project Window (Boundary Scan)

After the FPGA successfully programs, the Boundary Scan pane displays Program Succeeded. The FPGA application is now executing on the board.

8. Select File»Close Project, and save all changes.

4. Formatting the PROM

Before generating the PROM file, you must create the FPGA bitstream file. The FPGA provides an output clock, CCLK, when loading itself from an external PROM. To format the PROM, connect the USB cable to the NI Digital Electronics FPGA Board, apply power to the board, and move the power switch to the ON position.

1. In the Processes window, select the Processes tab.

2. Right-click Generate Programming File and select Properties.

3. In the Process Properties - Configuration Options window that opens, select Configuration Options as the category.

4. Using the Configuration Rate pull-down menu, select 25. This sets the internal CCLK oscillator to a frequency of 25 MHz. Refer to specifications in the NI Digital Electronics FPGA Board User Manual for the maximum frequency of the Digital Electronics FPGA Board. Do not select or alter the other options.

5. Click OK to generate the program file. The Transcript pane of the project window will display the programming progress.

6. In the Processes window, expand Configure Target Device, then double-click Generate PROM/ACE File. This updates all question marks, , with checkmarks, , indicating the successful configuration and generation of files and associated devices.

The Transcript pane of the project window displays the configuration progress. The compilation takes several minutes.

The iMPACT - Welcome to iMPACT window opens.

NOTE If the iMPACT - Welcome to iMPACT window does not open, launch iMPACT by selecting Start»Programs»Xilinx ISE Design Suite»ISE»Accessories»iMPACT. If you are prompted to create a new .jpf file, click Cancel.

7. In the Flows pane, double-click PROM File Formatter. The iMPACT - Prepare PROM Files window will open.

A. Select Xilinx PROM as the target PROM type.

B. Select MCS , the Intel Hex format, as the PROM File Format.

C. Leave the Checksum Fill Value as FF.

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D. Enter MyPlatformFlash in the PROM File Name text box.

E. Enter the location of the directory, x:Xilinx, where x is the drive that you installed the directory.

Click Next.

8. In the iMPACT - Select PROM/Flash Mode window, select I am using a Xilinx PROM in Serial Mode.

Click Next.

9. In the iMPACT - Specify Xilinx PROM Device window, select xcf as the PROM (bits), and xcf04s [4 M] from the pull-down menu. This selects the XCF04S platform flash PROM on the Digital Electronics FPGA Board.

10. Click Add to move your PROM selection to the window. Do not select any other options

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Click Next.

11. In the iMPACT - File Generation Summary window that opens, click Finish. The PROM Formatter opens the Add Device alert, which prompts for the name(s) of the FPGA configuration bitstream file(s).

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Click OK to select the files.

A. Select the main.bit configuration file in the Add Device window. Click Open.

You have the option of selecting additional device files. Because you do not need another device file, click No.

B. Click OK.

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When the PROM formatting completes, iMPACT presents the current settings by showing the PROM, the selected FPGA bitstream(s), and the amount of PROM space consumed by the bitstream. The following figure shows the example for a single FPGA bitstream stored in an XCF04S platform flash PROM.

PROM File Formatter

12. On the iMPACT menu bar, select Operations»Generate File to generate the PROM file. After the PROM file is created, the PROM File Formatter pane displays PROM File Generation Succeeded.

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Select File»Close Project, and save all changes.